Phase-locked loop (PLL) circuits are used in a variety of radio, telecommunications, computers, and other electronic applications. PLL clock switchover is a mechanism that enables a backup clock to clock the phase-locked loop in the event the primary clock to the PLL stops functioning in order to ensure reliability of PLL systems. The use of a phase-locked loop clock switchover creates more reliable systems compared to systems that does not support switchover, especially in networking systems.
Typically PLL clock switchover is implemented using a clock loss detection circuit. The clock loss detection circuit can introduce glitches in the output signal due to the combination of the circuit path and possible clock skew introduced into the clock loss detection circuit. These glitches can be interpreted by the PLL circuit to be a clock loss signal, which in turn can trigger a false clock switchover by the PLL. In other words, the phase-locked loop can unintentionally switch to the backup clock at times when the primary clock is still functional. The probability of these glitches occurring increases as designs are ported to more advanced process technologies that have increased process, temperature, and voltage variations. In addition, the complexity of typical clock switchover circuit designs contributes to slower response time, which in turn translates to lower maximum operating frequency.
It is in this context that embodiments of the invention arise.